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• LDOs are linear regulators and therefore their efficiency is lower than switching regulators.

LDO是線性穩壓器，因此它的效率通常比開關式穩壓器的效率低

• To get the most out of your LDO application

為要使LDO應用達到最佳化

• the LDO power dissipation needs to be carefully considered

需要仔細考慮LDO的功耗

• So let’s examine LDO power dissipation in more detail.

讓我們來看看LDO功率耗散的情形

• When choosing an LDO

選擇LDO時

• the maximum LDO input voltage range and LDO current capability are important factors to consider.

首先要考慮的是LDO的最大輸入電壓範圍和LDO電流輸出的能力

• But, larger current or larger voltage drop across the LDO

然而，較大的電流或較大的LDO電壓降

• quickly leads to higher device power dissipation

立即導致較高的元件功率損耗

• This plot shows the relation between LDO power dissipation, LDO voltage drop and LDO current

此圖顯示的是在特定的功耗值下，所允許的LDO電壓降與LDO電流之關係

• When power dissipation increases,

當功耗增加時

• The LDO package needs to be able to handle this power dissipation.

LDO封裝的散熱功能也必須能夠配合

• The power dissipation in the LDO is determined by the voltage drop across the LDO

LDO的功耗是由跨於LDO上的電壓降乘以流過LDO的電流而決定

• multiplied by the current passing through the LDO.

LDO的功耗是由跨於LDO上的電壓降乘以流過LDO的電流而決定

• This power is dissipated in the LDO pass element, which heats the silicon die.

功率主要是損耗在LDO的導通元件，使矽晶粒變熱。

• But how much power can you actually dissipate in the LDO?

但是您究竟能讓LDO損耗多少功率呢

• This depends on the IC package, the PCB layout and the ambient temperature.

這就取決於IC封裝、PCB佈局、和它的環境溫度

• Let’s have a look at some examples.

一起來看看一些例子！

• Here is a drawing of the small SOT23 package in a normal layout.

這是一個在一般佈局下的小型SOT23封裝圖

• When you look inside the package you can see that the center pin is connected to the die mounting lead frame.

若你能透視此封裝，就可以看到中心接腳是連接到貼著晶粒的導線架

• The silicon die is mounted underneath on this center pin lead frame.

矽晶粒是貼著於中心接腳導線架的下方

• When the silicon die is becoming hot

當矽晶粒變熱時

• this heat will be transferred to several parts of the package:

熱能會被傳送到封裝的幾個部分

• Some heat goes through the plastic directly to the ambient.

有一些熱能穿過塑料直接到周圍的環境

• Some heat goes through the pins to the PCB copper and then to the ambient.

有一些熱能則經過接腳而到PCB的銅線，然後再到周圍的環境

• Due to the thin bonding wires

由於外側接腳與矽晶粒之間的接合線非常細

• he outer pins do not have a good thermal connection with the silicon die,

熱能傳導並不好

• and their heat transfer to the PCB is limited

所以透過它們傳導到PCB的熱能很有限

• The center ground pin has a good thermal connection to the silicon die

中心接地接腳與矽晶粒之間的熱能傳導很好

• so more heat is transferred via this pin

較多的熱能是透過此接腳傳導出去

• To improve the cooling capabilities of this package

為改善此封裝的散熱能力

• it is important to add some extra copper to the pins

最好能在PCB上和所有接腳相接處都加寬銅線寬度

• especially to the center ground pin

尤其是到中心接地的接腳

• With improved layout, more power can be dissipated without overheating the silicon die

改善PCB佈局後，就能傳導更多的熱能，以免矽晶粒發生過熱現象

• Here is a different IC package: the popular SOP-8 package with exposed pad.

再看另一種IC封裝：這是常用的、有散熱焊盤的PSOP-8封裝

• In this package, the silicon die is mounted on a separate copper pad

在此封裝，矽晶粒被貼著於一個分離的銅盤

• which has an exposed surface at the bottom of the package

而它的另一面露出在封裝的底部

• In the PCB layout

在PCB佈局時

• this exposed pad should always be connected to a copper area underneath the IC

此裸露銅盤總是直接連於IC下方的銅線

• When the die gets hot

當晶粒變熱

• some heat will flow through the plastic package and some heat will flow through the pins.

有些熱能會流過塑料的封裝，而有些會流過接腳

• However, the majority of heat will flow through the exposed pad,

然而，大多數的熱能會是流過此裸露銅盤

• provided there is enough PCB copper connected to it

只要PCB有夠大的銅線與它相連

• It is therefore important to connect sufficient copper to the exposed pad,

因此有夠寬的銅線連接到此裸露銅盤更加重要

• to allow more heat flow via this route

好讓更多的熱能可經由此路線傳導出去

• When you use a multi-layer PCB,

若您是使用多層的PCB

• you can add several vias under the exposed pad which can connect to the PCB inner layers

您可以在裸露銅盤下方加上幾個通孔，以連接到PCB的內層

• These will act as effective heat sinks

其功效如同散熱片

• and allows you to dissipate more power in this package.

有助於將此封裝內更多的熱能傳導出去

• So how much power can you dissipate in each package?

所以在一個封裝內，您究竟能損耗多少功率呢？

• You can calculate the allowed power dissipation by dividing the allowed temperature difference

您可藉由將最大接面和最大環境溫度的差除以接面和環境之間的熱阻來計算

• between junction and ambient by the thermal resistance between junction and ambient.

您可藉由將最大接面和最大環境溫度的差除以接面和環境之間的熱阻來計算

• The thermal resistance value - theta junction amaient is shown in the datasheet,

熱阻值 (θJA ) 列於規格書上

• but keep in mind that this value is based on the JEDEC method

然而要留意的是，根據JEDEC方法而得的熱阻值

• which can be a bit conservative

較偏保守

• Here are some practical power dissipation limits for various package types

這裡列出各種封裝類型，和他們實際的功耗限制

• based on a normal PCB layout

這裡列出各種封裝類型，和他們實際的功耗限制

• with some extra copper connected to the package pins and thermal pad

此功耗限制是根據一般的PCB佈局、

• a maximum PCB ambient temperature of 60℃

最大PCB環境溫度為60 ℃

• and a maximum silicon die temperature of 125 ℃

和最大矽晶粒溫度為125 ℃ 而得

• If your ambient temperature is lower

若您實際的環境溫度較低

• the power dissipation can be higher.

最大功耗就可以高一點

• If your PCB is small, or there are other hot components nearby

若您的PCB較小，或者附近尚有其他的熱元件

• the maximum power dissipation may be less

最大功耗就可能較低

• I hope you now have a better understanding

希望現在您對LDO的功率損耗及散熱條件有更多的了解

• about power dissipation and thermal condistions to LDOs

希望現在您對LDO的功率損耗及散熱條件有更多的了解

如果您想更多了解立錡LDO產品

請點擊在左側的鏈結

• or visit Richtek websit at:

或上立錡官網www.richtek.com

• www.richtek.com

或上立錡官網www.richtek.com

LDOs are linear regulators and therefore their efficiency is lower than switching regulators.

LDO是線性穩壓器，因此它的效率通常比開關式穩壓器的效率低

B2 中高級 中文 功率 電流 環境 溫度 電壓 傳導

# LDO功率耗散 (LDO Power Dissipation)

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jmkuoa 發佈於 2021 年 01 月 14 日