Name: PCI Express (PCI Express)
Uploaded: 2021-01-14T05:39:28.000Z
Duration: 47 min 19 s
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PCI Express, officially abbreviated as PCIe, is a high-speed serial computer expansion

bus standard designed to replace the older PCI, PCI-X, and AGP bus standards. PCIe has

numerous improvements over the aforementioned bus standards, including higher maximum system

bus throughput, lower I/O pin count and smaller physical footprint, better performance-scaling

for bus devices, a more detailed error detection and reporting mechanism), and native hot-plug

functionality. More recent revisions of the PCIe standard support hardware I/O virtualization.

The PCI Express electrical interface is also used in a variety of other standards, most

notably in ExpressCard which is a laptop expansion card interface, and in SATA Express which

is a computer storage interface. Format specifications are maintained and developed

by the PCI-SIG, a group of more than 900 companies that also maintain the conventional PCI specifications.

PCIe 3.0 is the latest standard for expansion cards that is in production and available

Conceptually, the PCIe bus is like a high-speed serial replacement of the older PCI/PCI-X

bus, an interconnect bus using shared address/data lines.

A key difference between PCIe bus and the older PCI is the bus topology. PCI uses a

shared parallel bus architecture, where the PCI host and all devices share a common set

of addresscontrol lines. In contrast, PCIe is based on point-to-point topology, with

separate serial links connecting every device to the root complex. Due to its shared bus

topology, access to the older PCI bus is arbitrated, and limited to one master at a time, in a

single direction. Furthermore, the older PCI clocking scheme limits the bus clock to the

slowest peripheral on the bus. In contrast, a PCIe bus link supports full-duplex communication

between any two endpoints, with no inherent limitation on concurrent access across multiple

endpoints. In terms of bus protocol, PCIe communication

is encapsulated in packets. The work of packetizing and de-packetizing data and status-message

traffic is handled by the transaction layer of the PCIe port. Radical differences in electrical

signaling and bus protocol require the use of a different mechanical form factor and

expansion connectors; PCI slots and PCIe slots are not interchangeable. At the software level,

PCIe preserves backward compatibility with PCI; legacy PCI system software can detect

and configure newer PCIe devices without explicit support for the PCIe standard, though PCIe's

new features are inaccessible. The PCIe link between two devices can consist

of anywhere from 1 to 32 lanes. In a multi-lane link, the packet data is striped across lanes,

and peak data-throughput scales with the overall link width. The lane count is automatically

negotiated during device initialization, and can be restricted by either endpoint. For

example, a single-lane PCIe card can be inserted into a multi-lane slot, and the initialization

cycle auto-negotiates the highest mutually supported lane count. The link can dynamically

down-configure the link to use fewer lanes, thus providing some measure of failure tolerance

in the presence of bad or unreliable lanes. The PCIe standard defines slots and connectors

for multiple widths: ×1, ×4, ×8, ×16, ×32. This allows PCIe bus to serve both cost-sensitive

applications where high throughput is not needed, as well as performance-critical applications

such as 3D graphics, networking, and enterprise storage.

As a point of reference, a PCI-X device and PCIe device using four lanes, Gen1 speed have

roughly the same peak transfer rate in a single-direction: 1064 MB/sec. The PCIe bus has the potential

to perform better than the PCI-X bus in cases where multiple devices are transferring data

simultaneously, or if communication with the PCIe peripheral is bidirectional.

Interconnect PCIe devices communicate via a logical connection

called an interconnect or link. A link is a point-to-point communication channel between

two PCIe ports, allowing both to send/receive ordinary PCI-requests and interrupts. At the

physical level, a link is composed of one or more lanes. Low-speed peripherals use a

single-lane link, while a graphics adapter typically uses a much wider 16-lane link.

Lane A lane is composed of two differential signaling

pairs: one pair for receiving data, the other for transmitting. Thus, each lane is composed

of four wires or signal traces. Conceptually, each lane is used as a full-duplex byte stream,

transporting data packets in eight-bit 'byte' format, between endpoints of a link, in both

directions simultaneously. Physical PCIe slots may contain from one to thirty-two lanes,

in powers of two. Lane counts are written with an × prefix, with ×16 being the largest

The bonded serial format was chosen over a traditional parallel bus format due to the

latter's inherent limitations, including single-duplex operation, excess signal count and an inherently

lower bandwidth due to timing skew. Timing skew results from separate electrical signals

within a parallel interface traveling down different-length conductors, on potentially

different printed circuit board layers, at possibly different signal velocities. Despite

being transmitted simultaneously as a single word, signals on a parallel interface experience

different travel times and arrive at their destinations at different moments. When the

interface clock rate is increased to a point where its inverse is shorter than the largest

possible time between signal arrivals, the signals no longer arrive with sufficient coincidence

to make recovery of the transmitted word possible. Since timing skew over a parallel bus can

amount to a few nanoseconds, the resulting bandwidth limitation is in the range of hundreds

of megahertz. A serial interface does not exhibit timing

skew because there is only one differential signal in each direction within each lane,

and there is no external clock signal since clocking information is embedded within the

serial signal. As such, typical bandwidth limitations on serial signals are in the multi-gigahertz

range. PCIe is just one example of a general trend away from parallel buses to serial interconnects.

Other examples include Serial ATA, USB, SAS, FireWire and RapidIO.

Multichannel serial design increases flexibility by allocating slow devices to fewer lanes

A PCIe card fits into a slot of its physical size or larger, but may not fit into a smaller

PCIe slot. Some slots use open-ended sockets to permit physically longer cards and negotiate

the best available electrical connection. The number of lanes actually connected to

a slot may also be less than the number supported by the physical slot size.

An example is a ×16 slot that runs at ×4. This slot will accept any ×1, ×2, ×4, ×8,

or ×16 card, but provides only ×4 speed. Its specification may read: ×16; "×size

@ ×speed" notation is also common. The advantage is that such slot can accommodate a larger

range of PCIe cards without requiring motherboard hardware to support the full transfer rate.

Pinout The following table identifies the conductors

on each side of the edge connector on a PCI Express card. The solder side of the printed

circuit board is the A side, and the component side is the B side. PRSNT1# and PRSNT2# pins

must be slightly shorter than the rest, to ensure that a hot-plugged card is fully inserted.

The WAKE# pin uses full voltage to wake the computer, but must be pulled high from the

standby power to indicate that the card is wake capable.

Power All sizes of ×4 and ×8 PCI Express cards

are allowed a maximum power consumption of 25 W. All ×1 cards are initially 10 W;

full-height cards may configure themselves as 'high-power' to reach 25 W, while half-height

×1 cards are fixed at 10 W. All sizes of ×16 cards are initially 25 W; like ×1 cards,

half-height cards are limited to this number while full-height cards may increase their

power after configuration. They can use up to 75 W, though the specification demands

that the higher-power configuration be used for graphics cards only, while cards of other

purposes are to remain at 25 W. Optional connectors add 75 W or 150 W power

for up to 300 W total. Some cards are using two 8-pin connectors, but this has not been

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PCI Express (PCI Express)

physical

express

layer

rate