Ever since people have identified it as a roadblock in Nvidia's AI chip production and thus its stock price.

從那時起，人們就認定它是 Nvidia AI 芯片生產的攔路虎，進而影響其股價。

TSMC has accelerated construction on several advanced packaging fabs across Taiwan to unblock this plug.

臺積電已經加快了臺灣幾座先進封裝廠的建設速度，以疏通這一堵塞。

At the same time, they and the rest of the industry are moving forward on an interesting technology that not only panels.

與此同時，他們和行業內的其他企業正在推進一項有趣的技術，這項技術不僅可以安裝面板，而且還可以安裝在其他設備上。

Chips on panels.

面板上有芯片。

In this video, we're going to talk about this new thing on the semiconductor horizon.

在本視頻中，我們將討論半導體地平線上的這一新事物。

The chiplet-slash-tile approach is a cost-saving one.

芯片-斜面-瓦片法是一種節約成本的方法。

We fabricate chiplets using the appropriate node and then integrate them all together inside a single package.

我們使用適當的節點製造芯片，然後將它們集成在一個封裝內。

This is in contrast to a monolithic chip where a node makes the whole chip all at once.

這與單片式芯片不同，單片式芯片是由一個節點一次性製造整個芯片。

The advantage of chiplets is that only the most complicated part of the package needs to be made by the most advanced node, which suffers the lowest yields.

芯片的優勢在於，只需由最先進的節點製造封裝中最複雜的部分，而這部分的產量最低。

Not every part of the chip needs an N3E node.

並非芯片的每個部分都需要 N3E 節點。

Another advantage of chiplets has to do with design migration.

芯片組的另一個優勢與設計遷移有關。

Thanks to the AI boom, we're seeing several chipmakers, Nvidia foremost, move to an annual refresh cycle.

由於人工智能的蓬勃發展，我們看到幾家芯片製造商，尤其是 Nvidia，開始採用年度更新週期。

Being able to update just the most value-added part of the package without redoing the whole thing is a nice perk.

只需更新套裝軟體中最有價值的部分，而無需重新制作整個套裝軟體，這是個不錯的好處。

Roughly speaking, the industry has two methods-slash-philosophies for integrating these chiplet pieces together. 2.5D and 3D integration.

粗略地說，業界有兩種將這些芯片片集成在一起的方法--滑動理念。2.5D 和 3D 集成。

And before we start, I do want to note that the semiconductor packaging industry's naming conventions are chaotic.

在我們開始之前，我想指出的是，半導體封裝行業的命名規則非常混亂。

The standardization is not that great.

標準化程度不高。

What follows are rough definitions.

以下是粗略的定義。

Let us start with 3D.

讓我們從 3D 開始。

We just stack these puppies vertically.

我們只需垂直堆放這些小傢伙。

This can offer the smallest size package, fastest connections, and so on.

這可以提供最小尺寸的包裝、最快的連接等。

But 3D has issues like heat retention and failure analysis.

但 3D 存在熱滯留和故障分析等問題。

As in, we can't see into the package.

就像我們無法看到包裹裡的東西一樣。

So the industry introduced what is called 2.5D integration.

是以，業界推出了所謂的 2.5D 集成。

This is where we package disparate parts of the system, digital logic, the memory input and output, side by side on top of a substrate.

在這裡，我們將系統的不同部分、數字邏輯、內存輸入和輸出並排封裝在一個基板上。

Early on, 2.5D was seen as a mere layover on the path towards true 3D integration.

早期，人們認為 2.5D 只是實現真正 3D 集成道路上的一個過渡。

But that is no longer the case.

但現在情況已不再如此。

Today's high might, for example, 3D integrate the memory chips, big stacks of what we call high-bandwidth memory.

例如，如今的高功率存儲器採用 3D 集成內存芯片，即我們所說的高帶寬內存大堆棧。

That HBM will then be integrated side by side with the chip's other portions using 2.5D.

然後，HBM 將使用 2.5D 技術與芯片的其他部分並排集成。

TSMC has said that by 2027, you might see systems with 12 or more stacks of these little guys.

臺積電表示，到 2027 年，你可能會看到擁有 12 層或更多這些小傢伙的系統。

One major concern with the chiplet approach has been communication.

芯片組方法的一個主要問題是溝通。

The whole system can only work as fast as its slowest component.

整個系統的運行速度只能與其最慢的組成部分相當。

How are we going to have these different chiplets communicate with one another?

我們如何讓這些不同的芯片相互通信？

We can use layers of copper interconnects to redistribute signals horizontally across the system package.

我們可以使用多層銅互連，在整個系統封裝中橫向重新分配信號。

We call this the redistribution layer or RDL and they are immensely valuable.

我們稱之為再分佈層或 RDL，它們具有巨大的價值。

RDLs have another major use case.

RDL 還有另一個主要用途。

If a chip die has many densely packed connections, often the case for smaller chips, the connections are too small to match up with the larger, solder balls through which the chip communicates with the outside world.

如果芯片裸片上有許多密集的連接點（通常是較小的芯片），這些連接點就會太小，無法與較大的焊球相匹配，而芯片就是通過這些焊球與外界通信的。

RDLs can help distribute or fan out these connections, matching size to size.

RDL 可以幫助分佈或分散這些連接，使大小匹配。

The ability to fan out was one of TSMC's breakthrough packaging offerings to Apple with their integrated fan out or info technology.

扇出功能是臺積電利用其集成扇出或信息技術為蘋果公司提供的突破性封裝產品之一。

These RDL layers can either sit on top of, below, or be a part of what we call an interposer.

這些 RDL 層既可以位於中間層之上，也可以位於中間層之下，或者是我們所說的中間層的一部分。

You can think of it as like a PCB and they do sort of serve similar purposes.

你可以把它想象成印刷電路板，它們確實有類似的作用。

That interposer in turn sits on top of a substrate.

中間膜又位於基底之上。

Traditionally, the substrate provides the package's mechanical backbone.

傳統上，基材是封裝的機械支柱。

In other words, it keeps the delicate silicon die from bending.

換句話說，它能防止脆弱的硅芯片彎曲。

The chip still has to communicate with the PCB below it.

芯片仍需與下面的 PCB 板通信。

So, this substrate and the interposer must also have through vias, which are vertical copper interconnects, running through them.

是以，這種基板和插層還必須有通孔（垂直銅互連）穿過。

So good rule of thumb, RDLs are horizontal while through vias are vertical.

是以，好的經驗法則是，RDL 是水準的，而通孔是垂直的。

Since the packaging industry is chaos, we should not always expect the interposer and substrate to be distinct separate things.

由於包裝行業比較混亂，我們不應該總是期望中間膜和基材是截然不同的兩類東西。

Sometimes the interposer does substrate-like things, invalidating the need for a separate substrate.

有時，插層會做類似基底的事情，從而使單獨基底的必要性失效。

It is all dependent on the product's spec and design.

這完全取決於產品的規格和設計。

Late last year, Intel announced glass quote unquote core substrate panels for use in advanced packaging solutions.

去年年底，英特爾發佈了用於先進封裝解決方案的玻璃引芯基板面板。

To repeat, the substrate helps keep the die mechanically stable.

重複一遍，基底有助於保持模具的機械穩定性。

Most often, it was made from a core panel of metal, ceramic, or organics.

它通常由金屬、陶瓷或有機物芯板製成。

The cores are then covered with layers of other stuff.

然後再用其他材料層層覆蓋核心。

The first Intel CPUs had substrates of ceramic.

首批英特爾 CPU 的基板是陶瓷。

Then, in 1995, Intel led an industry change from ceramics to organics like epoxy resin, with glass fibers woven into them.

隨後，在 1995 年，英特爾引領行業從陶瓷轉向環氧樹脂等有機材料，並在其中編織了玻璃纖維。

The new change that Intel is proposing here is to use substrate panel cores of pure glass.

英特爾在此提出的新變化是使用純玻璃的基板面板內核。

This is because of glass's physical properties.

這是因為玻璃具有物理特性。

Glass offers better heat tolerances and a superflat surface which can support a denser network of interconnects and easier to inspect the package for issues.

玻璃具有更好的耐熱性和超平表面，可以支持更密集的互連網絡，也更容易檢查封裝是否有問題。

This has been a major problem with these complicated packages.

這一直是這些複雜套裝軟體的一個主要問題。

How do you look into them?

你是如何調查它們的？

Anyway, it was a brief announcement and so did not get much attention.

無論如何，這只是一個簡短的公告，是以沒有引起太多關注。

But Intel has long been, and still is, a trendsetter.

但長期以來，英特爾一直是潮流的引領者，現在依然如此。

I give them full credit for kicking this off.

我對他們的貢獻給予充分肯定。

So TSMC and Samsung have in turn followed on.

是以，臺積電和三星也緊隨其後。

Substrates are relatively simple structures.

基質結構相對簡單。

Glass has a few tricky things, which we can talk more about later.

玻璃有一些棘手的問題，我們稍後再談。

But it will probably work.

但它可能會成功。

Can a glass panel, however, replace the far more complicated silicon interposer?

然而，玻璃面板能否取代複雜得多的硅質內插板呢？

Today, the industry makes almost all of their interposers from silicon wafers, like the ones to make the silicon dye.

如今，業界幾乎所有的中間膜都是用硅晶片製造的，比如製造硅染料的晶片。

In many ways, silicon is a fine choice.

在許多方面，硅都是一個不錯的選擇。

The technology is super mature and offers the best performance.

這項技術已經非常成熟，並能提供最佳性能。

As in, it lets us produce the densest layers of interconnects.

也就是說，它能讓我們生產出最密集的互連層。

The techniques have been around for decades now.

這些技術已經存在了幾十年。

Silicon also lets us put devices like transistors right inside the interposer.

硅還能讓我們將半導體等器件直接放入中間膜中。

Such interposers are called active interposers.

這種內插器被稱為主動內插器。

One without devices and has just the interconnects is called, naturally, a passive interposer.

沒有器件、只有互連的插層自然被稱為無源插層。

So that's the upsides.

這就是好處。

What are the downsides?

有什麼缺點？

One major issue is that using silicon is expensive and a bit wasteful.

一個主要問題是，使用硅的成本很高，而且有點浪費。

It means making interposers from the same massive silicon crystals that we the Czochralski process where we slowly pull a crystal out of a melt.

這意味著，我們可以用與 Czochralski 工藝相同的大塊硅晶體來製造中間膜，在 Czochralski 工藝中，我們可以慢慢地從熔體中拉出晶體。

Then after that, we must cut, polish, and prepare that crystal into wafers in a series of expensive steps.

之後，我們必須通過一系列昂貴的步驟，將晶體切割、拋光和製備成晶片。

This could potentially hurt yield, which is not ideal.

這可能會損害收益率，這並不理想。

Not to mention, drilling through vias into silicon is a complicated process.

更不用說，在硅中鑽孔是一個複雜的過程。

This is because the wires going through the vias are made from copper, and if we don't apply protective liners, then the copper diffuses into silicon.

這是因為穿過通孔的導線是由銅製成的，如果我們不使用保護襯墊，銅就會擴散到硅中。

It works, but it sometimes feels like overkill.

它很有效，但有時會讓人覺得矯枉過正。

Another economics-related problem is that the silicon crystals are round and can only be about 200mm or 300mm wide, the silicon industry's standard wafer size.

另一個與經濟有關的問題是，硅晶體是圓形的，寬度只能達到約 200 毫米或 300 毫米，這是硅業的標準晶片尺寸。

This limits how many interposers you can cut out from a single silicon crystal.

這就限制了從單個硅晶體中切割出多少個內插器。

The big NVIDIA Blackwell chips need big rectangular interposers and you can only get like four of them out of a single 300mm wafer.

大型英偉達™（NVIDIA®）Blackwell 芯片需要大型矩形內插器，而一個 300 毫米的晶圓只能裝四個內插器。

Moreover, there is some wasted space.

此外，還有一些浪費的空間。

Cut out a bunch of squares or rectangles out of a round wafer and you are left with some wasted silicon at the edges.

在圓形硅片上切出一堆正方形或長方形，就會在邊緣留下一些浪費的硅片。

So if you can make interposers out of a rectangular panel, you get some major cost savings.

是以，如果能用矩形面板製作內插板，就能大大節約成本。

You can better utilize the space and in some cases, get up to 8x more usable panels, which cuts per panel cost.

您可以更好地利用空間，在某些情況下，可用面板最多可增加 8 倍，從而降低每塊面板的成本。

The issue is figuring out what material we should make the panels out of.

問題是我們應該用什麼材料來製作面板。

Because there are always tradeoffs.

因為總要有所取捨。

Since the mid-2010s, the industry has been investigating organic interposers.

自 2010 年代中期以來，業界一直在研究有機插芯。

Interestingly enough, actually finding out what these organics in the organic interposers are is a bit of a chore.

有趣的是，要想知道有機插層中的這些有機物到底是什麼，還真有點困難。

The best that I can do is that they are composed of multiple layers like how they make PCBs today.

我只能說，它們是由多層電路板組成的，就像現在的印刷電路板一樣。

At their core, you might use a material like bismaleamide triazine resin or BT epoxy, which is already used for circuit boards.

在其核心部分，您可以使用雙馬來酰胺三嗪樹脂或 BT 環氧樹脂等材料，這些材料已用於電路板。

Another is FR-4 substrate, another epoxy resin with fiberglass woven into it.

另一種是 FR-4 基材，這是一種環氧樹脂，其中編織有玻璃纖維。

FR-4 is particularly known for its resistance to flames.

FR-4 尤其以耐燃性著稱。

The FR stands for flame retardant.

FR 代表阻燃。

It's pretty tough and strong and holds up well in humidity.

它非常堅硬結實，在潮溼的環境中也能保持良好的性能。

Organic interposers are cheaper than silicon interposers, not just in financial cost but complexity cost as well.

有機插芯比硅插芯便宜，不僅是經濟成本，還有複雜性成本。

They are easy to process.

它們很容易處理。

You don't need particular steps.

您不需要特別的步驟。

And so on.

等等。

But organics have two major downsides.

但有機物有兩大缺點。

First, the performance is worse.

首先，性能更差。

The smallest possible width of the lines and the spacing between them is about 2 microns.

線條的最小寬度和間距約為 2 微米。

So we cannot achieve the same interconnect density as with silicon.

是以，我們無法實現與硅相同的互連密度。

Second, there is a warpage problem.

其次是翹曲問題。

Semiconductors get hot and managing those thermals gets far trickier with these packages.

半導體會發熱，管理這些熱量對於這些封裝來說就變得更加棘手。

When any substances get exposed to heat, their size changes.

任何物質受熱後，其大小都會發生變化。

That change is determined by a factor known as Coefficient of Thermal Expansion or CTE.

這種變化由一個稱為熱膨脹係數或 CTE 的係數決定。

No relation to chronic traumatic encephalopathy, the brain disorder caused by repeated head trauma due to things like NFL tackles or studying advanced packaging terminologies.

與慢性外傷性腦病沒有任何關係，慢性外傷性腦病是一種因反覆頭部外傷（如美國橄欖球聯盟的擒抱動作）或學習高級包裝術語而導致的腦部疾病。

Organic interposers are not as good as conducting away and dissipating heat as silicon ones are.

有機插層的導熱和散熱性能不如硅插層。

Thus you tend to get hotspots inside the package, which require intense computations to identify.

是以，套裝軟體內往往會出現熱點，需要進行大量計算才能識別。

And what is the problem with the hotspots?

熱點問題是什麼？

Well, the CTE of the organics are not matched up well with that of the silicon dye or the substrate.

有機物的熱膨脹係數與硅染料或襯底的熱膨脹係數不匹配。

So the hotspots make the organics warp, ruining the whole package.

是以，熱點會使有機物變形，破壞整個包裝。

Just like how organics came from the PCB industry, the microelectronics industry has long been familiar with glass panels.

就像有機玻璃源於印刷電路板行業一樣，微電子行業對玻璃面板也早已耳熟能詳。

We produce liquid crystal displays on top of them, layering on thin film transistors or TFTs on top of a precisely manufactured glass substrate.

我們在其上生產液晶顯示器，在精確製造的玻璃基板上分層安裝薄膜半導體或 TFT。

The panels used for these displays have to be extremely well crafted.

這些顯示器使用的面板必須製作精良。

They need to be very thin, maybe about 200 micrometers thick.

它們需要非常薄，大概 200 微米厚。

Yet at the same time, the panel has to be strong enough to resist falls.

與此同時，面板還必須足夠堅固，以抵禦墜落。

Oh, and as always, it needs to be affordable.

哦，和往常一樣，它需要經濟實惠。

Corning produces most of these glass panels.

康寧公司生產大部分此類玻璃面板。

In the 1960s, they invented and patented the fusion draw process, originally for making the windshields of cars.

20 世紀 60 年代，他們發明了熔融拉伸工藝，並申請了專利，該工藝最初用於製造汽車擋風玻璃。

The fusion draw is pretty crazy.

融合抽籤相當瘋狂。

You put molten glass into a V-shaped trough and then overflow it.

將熔化的玻璃放入 V 形槽，然後溢出。

The glass spills over both ends and then meet at the bottom of the V.

玻璃從兩端溢出，然後在 V 形底部匯合。

There they fuse, creating a sheet.

它們在那裡融合，形成一張薄片。

Amazing technology.

令人驚歎的技術

But with the LCD industry on the decline thanks to OLED's dominance, Corning has been doing R&D to see if their glass technologies can be applied to packaging.

但是，由於 OLED 的主導地位，LCD 行業正在走下坡路，康寧公司一直在進行研發，看看他們的玻璃技術能否應用到封裝領域。

Since 2010, teams at the 3D Systems Packaging Research Center at Georgia Tech have been investigating the possibility of using glass interposers for high performance computing.

自 2010 年以來，佐治亞理工學院 3D 系統封裝研究中心的團隊一直在研究將玻璃插層用於高性能計算的可能性。

To make one, you start with a special glass panel core.

製作時，首先需要一個特殊的玻璃板芯。

We then drill into that core thousands of through-glass vias or TGVs.

然後，我們在磁芯中鑽入數千個通孔（TGV）。

These TGVs are then filled with copper.

然後在這些 TGV 中填充銅。

And after that, we laminate RDLs and patterns onto both sides of the glass interposer core.

然後，我們將 RDL 和圖案層壓到玻璃插芯的兩面。

Glass is already used in a few applications like MEMS and RF, but high compute would be like going to the major leagues.

玻璃已經在微機電系統（MEMS）和射頻（RF）等一些應用中得到了應用，但高計算能力就像進入了大聯盟。

Glass offers many upsides.

玻璃有很多優點。

One of the problems with the organic interposers was warpage.

有機中間膜的問題之一是翹曲。

While it can still be a concern if your glass panels are very large, glass is nice because we can better adjust its CTE via its composition to better match it to the silicon die and the substrate below.

如果您的玻璃面板非常大，這仍然可能是一個問題，但玻璃是好東西，因為我們可以通過其成分更好地調整其 CTE，使其與硅芯片和下面的基底更好地匹配。

Glass's major downside, however, might be quite familiar to you.

不過，您可能對玻璃的主要缺點並不陌生。

Cracking.

咔嚓咔嚓

Just cutting the glass panel dies out of their big panels can be challenging.

僅從大面板上切割玻璃板模就很有挑戰性。

We use a mechanical saw to do this, and early tests have noticed that it to appear.

我們使用機械鋸來完成這項工作，早期的測試已經發現它的出現。

The industry has taken to call these cracks seware after the Japanese phrase meaning splitting of the back.

業內人士將這些裂縫稱為 seware，日語的意思是背部裂開。

Even the smallest cracks can propagate throughout the rest of the panel, basically ruining it.

即使是最細微的裂縫也會蔓延到面板的其他部分，基本上會毀壞面板。

Seware failures can happen either because of deep, sharp defects left behind by the cutting process, or because of tensile stresses from the various copper interconnect layers laminated onto its surfaces.

出現縫隙故障的原因可能是切割過程中留下的深而尖銳的缺陷，也可能是層壓在其表面的各種銅互連層產生的拉伸應力。

Japan's DISCO Corporation ran a few experiments and found a pretty nice method to avoid some seware failures, using a dicing blade made from diamond grit of a very specific size, and pulse lasers also did a fine job as well.

日本的迪思科公司進行了一些實驗，發現了一種很好的方法，可以使用由特定尺寸的金剛石砂礫製成的切割刀片來避免一些縫隙故障，而脈衝脈衝光也能很好地做到這一點。

Moreover, to work as a glass interposer, the panel must accommodate maybe tens of thousands of TGVs without cracking.

此外，要用作玻璃中間膜，面板必須能承受數萬次 TGV 的撞擊而不會破裂。

This is a major obstacle.

這是一個主要障礙。

The industry has investigated how to make these, from lasers to acids to just a straight up drill.

業界已經研究瞭如何製造這些東西，從脈衝光到酸性物質，再到直接的鑽頭。

And what techniques should we employ here?

我們在這方面應該採用什麼技巧呢？

Do we drill straight through?

我們要直接鑽過去嗎？

We call those through holes.

我們稱之為通孔。

Or do we stop short of the surface and ground down the opposite surface to reveal the via?

或者，我們是在表面停止，然後磨掉相反的表面，以揭示經脈？

That is a blind hole.

這是一個盲洞。

We have yet to find the right tool and technique for doing this at scale.

我們還沒有找到合適的工具和技術來大規模開展這項工作。

Such issues with panel warpage and cracking will open opportunities again in metrology.

面板翹曲和開裂等問題將再次為計量領域帶來機遇。

There are already some intriguing companies in the space, several of whom are pivoting over from the declining LCD panel world.

該領域已經出現了一些引人入勝的公司，其中有幾家是從日漸衰落的液晶面板領域轉過來的。

So panel-level packaging has been around for a while.

是以，面板級包裝已經存在了一段時間。

The question is whether or not the technology is finally about to hit the big time.

現在的問題是，這項技術是否終於要大顯身手了。

Intel has kicked off the race for glass substrates and I on glass interposers as well behind the scenes.

英特爾在幕後啟動了玻璃基板和玻璃中間膜的競賽。

But the rest of the industry is catching up.

但其他行業正在迎頭趕上。

It was news that TSMC spent about half a billion dollars to acquire an LCD panel fab in Tainan from Inolux.

有消息稱，臺積電斥資約 5 億美元從 Inolux 收購了位於臺南的一座液晶面板工廠。

They apparently intend to use it for advanced packaging purposes, which to me is panel-level packaging.

他們顯然打算將其用於高級包裝目的，在我看來，這就是面板級包裝。

Side note, the Taiwanese LCD industry's slow decline is an interesting trend.

題外話：臺灣液晶顯示器行業的緩慢衰退是一個有趣的趨勢。

For a write-up, go check out the newsletter Tim Coulpin's Position.

如需瞭解相關報道，請查閱通訊《Tim Coulpin's Position》。

He has done great analysis and reporting on this industry since before this channel even existed.

在這個頻道出現之前，他就已經對這個行業進行了很好的分析和報道。

Anyway, that panel-level packaging was so prominently featured by TSMC, ASC, and the rest of the industry at Semicon 2024 is another hint that this stuff is coming along.

無論如何，臺積電、ASC 和業界其他公司在 2024 年半導體展上如此突出地展示面板級封裝，再次暗示了這一技術的發展。

Some are even calling it inevitable.

有些人甚至認為這是不可避免的。

The challenges are formidable, but I expect these to start coming along in the near future two to three years.