It just prints out Hello World.

But it was over 170 lines long because it had tons of redundant code that I was able to remove by factoring it out into a couple subroutines.

But then when we tried running the program, it didn't work.

And as we saw in the last video, it didn't work, because when the computer jumps into a subroutine, it pushes the return address on to the stack, which is in memory.

And then, at the end of the subroutine, it pulls that return address off stacks so it could jump back from where it came.

Now our problem is that our computer doesn't actually have any RAM in it.

At address 0100 through 01 f f where the stack needs to be, or anywhere else, for that matter.

So let's fix that.

Let's add some ram.

This is the 62 to 56 parallel Ram chip.

Which of the 2 56 in the name indicates that it can store 256 killa bits, which, with eight bits per byte, means we get 32 kilobytes of data, so let's hook it up right now.

I'm just disconnecting the Arduino Omega Tau just to get that out of the way.

We can reconnect it later, but just to make it easier for you to see what's going on, I'll get it out of here right now.

And now if we look at the pin out for this Ram chip, we see it's actually very similar, in fact, almost identical to the wrong ship we have, which is which is very convenient because just like the rahm chip, it's got 15 address lines because it's also, you know, 32.

We have 32 K rahm and then a 32 K ram, and it's got the data lines, and the pin out is actually exactly the same.

So if I want to connect the Ram chip here to the data bus and the address bus, really adjusting to connect all the data lines over and all the address lines over, it's the way the Ram chip is hooked to the address bus and data bus, just the same as the Rahman and everything else.

We'll start by connecting power and ground, then I'll connect the address lines and the data lines.

Some hooking up, 15 address lines, a zero through a 14.

And, of course, we already have thes connected from the microprocessor, a 03 14 hooked to the rahm a zero through a 14.

And now I'm just hooking them the same.

A zero through a 14 lines over to the Ram chip.

Okay, so those are all the address lines connected Now, I just need to hook up the data lines and same thing here.

You know, we've got the eight data lines, of course, Already going from the microprocessor to the wrong chip.

I'm just extending those same 88 lines over to the Ram chip, and then we go in.

Now we've got all of the 15 address lines, plus the eight David lines hooked up.

So I've got all of our address and data lines plus course, our power and ground and the only pins now that are not hooked up are the right enable the chip select and the output enable pins.

That's right.

Enable output enable and chip select those control signals.

We need to hook up a swell.

So right enables pretty easy because that hooks right to the reed right pan on the microprocessor because the microprocessor has a read right signal that it outputs along with the data bus to say whether it's reading from the data bus.

We're writing to the data bus and that goes low when it's writing.

And then the right enable is an active low here.

So we could just hook that right.

Enable signal from the or the right of the rewrite signal from the microprocessor over to the right.

Enable input over here on the Ram chip.

Here we go.

So that's the right enable pin.

But how about output enable and chips elect?

Well, when do we want the Ram to actually be active?

Well, we only wanted to be active when the microprocessor is actually reading or writing from some address.

That's within the range for the Ram.

And of course, we know we want that to include our stack, which is 0100301 f f.

But you know, we want a larger range than that for Ram.

So this is the memory map that I've come up with for the computer right now where we've got you know the addresses because there's 16 bits of address coming off the microprocessor, So the address can go from 0000 through F f f f.

And right now, the way we've got this hooked up is the Rahm chip is taking up the upper half.

So any time that that most significant address bid and, you know, address 15 in time, that is high than the rahm is active.

And so the Rahm is taking up addresses from 8000 all the way through F f f f.

So the easy thing to do would be just to have the ram enabled whenever the rahm is not enabled.

That way, the Ram would take up the lower half of memory and Ron would take up the upper half of memory.

The only problem with that is that we need to have some address space here for for Io.

And in previous videos, we have this versatile interface adapter hooked up here on address 6000 through six years, their F 16 addresses that it responds to.

So we can't just stick our ram on this whole first half here, so the sort of easy thing to do is just to take up the first quarter of the address space with RAM from 00023 FFF.

Which means, you know, even though this is a 32 K RAM chip, it could potentially provide 32 k of address space.

We're actually only gonna use 16 K, and the reason to do that is, is, you know, frankly, because it's just easy to d'oh Essentially, what we can do is we can say, you know, the ramp should only be active when Address 15 and address 14 are both zero because of address 15 and 14 or zero.

Then that means were in this range from 0000 through three FFF.

So from a hardware perspective, it's It's very easy to detect.

When we're in that range and activate the Ram, you might say, Well, that's inefficient.

You know, there's there's, you know, we're wasting half of the ram that's on this chip.

We also have all of this address space here between fours years or zero and seven FFF that we're not using, except for the 16 addresses for for Io here and, you know, fair enough that is somewhat inefficient.

But you know, the trade off that we're making there is that the address decoding is easier.

You know, if we were to try to detect, you know, when the Rams should be active throughout this entire space except for that one little block there for Io Or maybe, well, maybe a little bit extra.

Um, the address decode logic that we would need to build to do that would be more complex.

And so there's a trade off to be made there, you know, how complex do we want her address decode logic to be versus how much Ram do we actually need?

And, you know, I think 16 k of RAM is probably going to be enough for anything that we would build with this computer.

But, you know, if you end up writing a program for this computer that needs more than 16 k of ram A, I'd be surprised, but being in haIf, it better be a pretty cool program, so I'd love to see it.

But until then, I I think no one needs more than 16 cave of memory.

So let's let's go ahead and do this.

That means right Now, this is what we've got hooked up.

Right?

We've got address.

Zero through address.

14 of the ram hooked up to address your arthritis.

14 of the processor.

We've got the data bus hooked up D 0 37 And then we hooked up the reed right pin on the microprocessor to the right.

Enable pin.

And what we're saying is we want the Ram to only be active when address 15 and address 14 are both low because of both of those are low.

Then that means were in this ranger at the first.

The top two bits of this address are both zeros.

Then that would mean that our address is gonna be somewhere between 0000 and three f f f.

So you know, that seems like it be easy enough to do.

We could simply hook up something like this because we've got the output enable, which is active low.

And we've got the chip select, which is active low.

And in order for the ram to actually out put anything on the bus, both of those have to be low.

So if we hook output unable to address 14 and we hook chip.

Select address 15.

Then the Rams not gonna output anything.

Unless where in, you know, again, we're in that range of, you know, that we want the ram to be from 0000 through three f f f now.

Technically, if address 14 is high and address 15 is low.

So we're in this range, then output enable wouldn't be active.

So would the ram would never out put anything on the bus, but potentially if if the processor is writing to an address in that range, it would actually write to RAM.

But, you know, we don't really care about that cause would be writing to a part of the ram or not using.

So that's fine.

So this this seems like it would be a pretty good approach.

Just hook address 14 brother microprocessor up to the output.

Enable signal and hook.

Address 15 up to the chip select signal.

And this should ensure that the ram is active on Lee in this address range.

Ah, but not so fast.

All this sounds good, but of course, reality is always a bit more complicated if we look at the data sheet for the 62 to 56.

The Ram chip.

It's got these timing diagrams that show various limitations in the timing of signals when doing a read or write under very circumstances.

And the 65 to processor also has timing diagrams where that show very slimming limitations.

And you know, we ought to take some time to study these timing diagrams to make sure we understand what those various limitations are to make sure that we're meeting them.

Otherwise, we could end up with them really hard to debug problems down the road.

For example, this is the reed cycle timing diagram for the Ram chip that we're using and what it's showing us isn't showing us how we would actually do a read from the Ram chip and you think about how Reed would work.

You think?

Well, okay, the microprocessor wants to read some data from the RAM, and so what it's gonna do is what wants to read from a particular address, puts that address out on the address bus, and that's what these green wires are.

And so those air hooked up ways hook those up to the ram.

So the Rams gonna have that input there from those address lines saying, OK, this is the address one read from, and then ultimately what we want is they want the Ram chip to then output.

Whatever data is stored at that address on the data bus, which of these blue wires that'll go back where the microprocessor could read it?

So on the surface, that seems pretty simple, right?

The microprocessor puts an address on the address lines, and then it reads the data from the data lines.

And of course, there's a couple control signals.

It also needs to get set up.

So the reed right signal that we just hooked up that's hooked up here to tell the Rand reading, not writing on.

And then we have the CIP Select and Output enable that activate the Ram when we're in the right range.

But it's not quite so simple, is just setting all those address lines and control signals and then immediately reading because it might actually take the Ram chip a little bit of time to get the data and haven't output on that on the data bus.

In a way, that is, that is valid.

And that is actually ah, bit of ah sort of an access delay that the Ram chip imposes.

So when the processor sets the address, it wants to read from and sets the control signals on the bus, the president actually still wait a little bit before it can read the valid data from the Ram.

And that's what this timing diagram is showing us.

What this is showing is that, you know, as time moves from left to right here, the process has got to set up the address lines before it can read the data.

And what what?

What we're seeing here is this is a representation of all 15 address line because the processor may not even set all 15 address lines instantaneously at the same moment.

But what this says is that at this point here, they're all set correctly, and what it says is a little bit later, The trip select line is set low, and then a little bit after that, the output enable Linus set low, and then we have to wait some additional time before the data is finally valid.

And in our case, we're saying Trip Select is connected to a 15 and output enable is connected to a 14 But notice that, you know, once the address line address is set correctly and the chips elect is low and the output enable is low, the Ram chip doesn't immediately spit out the data.

That's at that address.

It actually takes some amount of time before it starts spitting out any data and then a little bit more time before it actually spits out the right data.

The question is, how much time does it actually take here?

You know, we can see sometimes marked here.

So there's this ta a from when the address is set to when the data is valid, there's a T A C s from when chips like goes low toe when there's valid data.

And then there's this t o E.

From when output enable goes low toe when there's valid data.

And really, since both of these in our cases are connected, address lines a 14 and 15 we can really think of all of these things.

All of these events kind of happening at the same time because at some point the process is going to get the address set correctly and they'll have a valid address, including a 15 and a 14.

And so then the time between when the processor sets that address and when the data is valid is just whichever is sort of the longest of those three times, you know this Ta the t A C s or the T o e.

So what are those times?

Well, data sheet has this other table here for the read cycle times for under a sea characteristics.

And here we got TA, which is address access Time T A C s, which has chips elect to access time and T o E, which is output unable to output valid.

And each of those has a couple of times, depending on which actual, particular variety of the chip were using.

And I think I'm using the Dash seven version or actually says Dash 70.

But I I think that means we're looking at this middle column here, the Dash seven.

So those three times are 70 nanoseconds, 79 seconds or 40 nanoseconds.

The last one's a little bit quicker.

It doesn't matter.

We still have to wait for the longest of them, which is 70 nanoseconds.

So that means when the processor wants to read data for memory once it's set the address lines, including address 14 15.

In our case, it could take up to 70 Nana seconds before the Ram chip actually spits out valid data.

So how do we know if that's gonna be a problem for the 65 02 microprocessor?